This invention relates to semiconductor memory devices, and more particularly to techniques which are effective when utilized in, for example, a bipolar type RAM (random access memory) which is constructed on the basis of an ECL (emitter-coupled logic) circuit.
A bipolar type RAM constructed on the basis of an ECL circuit is employed as, for example, the cache memory or stack memory of a high-speed computer. Therefore, a high operating speed is required of such a bipolar type RAM. The bipolar type RAM is brought into a selected state in accordance with a chip select signal CS which is supplied as a control signal from outside by way of example. Further, in the bipolar type RAM brought into the selected state, the operation of writing data into a selected memory cell is selectively executed in accordance with a write enable signal WE.
The bipolar type RAM is described in, for example, the official gazette of Japanese Patent Application Laid-open No. 60487/1983.